Computers and other electronic systems often require multiple clock signals. Often, it is desirable to produce multiple clock signals based on a single clock signal. One conventional method of generating multiple clock signals is to use a phase-locked loop (PLL). A PLL circuit may receive a clock signal as an input, and produce one or more output clock signals from the input clock signal. Another conventional method of generating multiple clock signals is to use a clock divider circuit. A clock divider circuit may be configured to receive an input clock signal and produce an output clock signal of a lower frequency. The output clock signal may be produced by dividing the input clock signal by a predetermined ratio. A typical clock divider circuit may include several flip-flop circuits, and may be able to divide an input clock signal by one of several even-integer ratios (e.g., 2, 4, 6, etc.).
These frequency dividers and frequency multipliers (e.g., PLLs) are used for many different applications. In particular, frequency dividers are used to reduce the overall number of oscillators required on a given semiconductor chip, thereby making available additional room on the chip for additional functional circuitry. Often, a single oscillator circuit is provided that generates a master clock signal. One or more frequency dividers and/or multipliers are then used to generate clock signals having different frequencies. For example, one or more divide-by-two circuits may be used to divide the master oscillator clock frequency by a factor of 2, 4, 8, etc. Often, it is desirable to programmably divide the clock signal (e.g., to select the divider ratio at runtime by providing or selecting one or more signals indicating the desired divider ratio). This may be accomplished by, for example, dynamically selecting one output from a plurality of clock divider circuit outputs, or by changing the operation of one clock divider circuit in response to the selected divider ratio.
On problem with many conventional clock circuits relates to their duty cycle. Clock signals produced by many conventional clock circuits and/or clock divider circuits do not have a 50% duty cycle (e.g. the duration of the positive or “on” portion of the signal may be appreciably longer or shorter than the duration of the negative or “off” phase of the signal, so that the signal is not “on” for substantially 50% of the time). This may be less of a concern for low frequency systems and/or systems which use only one clock edge for triggering devices. However, in some higher frequency systems some devices may be triggered by the positive edge of the clock signal, while other devices may be triggered by the negative edge. In such systems, it may be critical for the clock signal to have a 50% duty cycle. For example, when a clock signal has a 2 nanosecond (ns) period and a 50% duty cycle, devices triggered by either clock edge have ins to complete operations. However, if the clock signal is asymmetrical (e.g., having a duty cycle of 40% “on” and 60% “off”) then devices triggered by of one clock edge may have less time to complete operations than devices triggered by the opposite clock edge. This may have a limiting effect when attempting to design systems that will utilize both clock edges for triggering devices.
Many clock divider circuits are configured primarily for dividing an input clock signal by an even-integer ratio (e.g., 2, 4, 6, etc.), as it is considered easier than dividing by an odd-integer ratio. Clock divider circuits that divide by odd-integer ratios are known in the art, but these circuits are often unable to achieve a duty cycle of 50%. Referring now to FIG. 1, a clock signal 101 is shown. Divided clock signal 102 is an output of a conventional divide-by-three clock divider employing counters or cascaded flip-flops. It can be seen that the duty cycle of signal 102 is approximately 66% (e.g., “on” for two input clock cycles and “off” for one input clock cycle). Such clock signals may be unsuitable for systems utilizing both clock edges, or where a 50% duty cycle is critical for other reasons. Furthermore, many conventional clock divider circuits require an input clock signal with a duty cycle of 50% in order to produce a duty cycle of 50% for odd-integer divider ratios
Therefore, a need exists to provide methods and circuits for programmable integer clock division with a 50% duty cycle for odd and even divide ratios. Furthermore, it is desirable to provide such clock division even when the input clock signal does not have a 50% duty cycle, and to use standard integrated circuit components.